In mobile products, the internal core voltages of the semiconductor devices need to be lowered in order to reduce the power consumption. Meanwhile, I/O buffers need to perform a level shift between the internal core voltage and the I/O voltage. A level shifter applicable to such an I/O buffer is disclosed in Patent Document 1.
FIG. 8 is a circuit diagram of the level shifter disclosed in Patent Document 1. In FIG. 8, the level shifter is formulated by PMOS transistors MP101, MP102, MP103, and MP104, NMOS transistors MN101 and MN102, and inverters INV101, INV102, and INV103. The PMOS transistor MP101 has its source connected to a power supply VDDQ and its gate connected to an output node N91 of a cross-connected section. The PMOS transistor MP102 has its source connected to a drain of the PMOS transistor MP101 and its gate connected to a node N93, which is an output of the inverter INV101. The NMOS transistor MN101 has its source grounded, its drain connected to a node N92, which is a drain of the PMOS transistor MP102, and its gate connected to the node N93, which is the output of the inverter INV101.
The PMOS transistor MP103 has its source connected to the power supply VDDQ and its gate connected to the node N92. The PMOS transistor MP104 has its source connected to a drain of the PMOS transistor MP103 and its gate connected to a node N94, which is an output of the inverter INV102. The NMOS transistor MN102 has its source grounded, its drain connected to the output node N91 of the cross-connected section, which is a drain of the PMOS transistor MP104, and its gate connected to the node N94.
The inverter INV101 has its input connected to an input terminal IN and receives power supply voltage VDD. The inverter INV102 has its input connected to the node N93, which is the output of the inverter INV101, and receives the power supply voltage VDD. The inverter INV103 has its input connected to the output node N91 of the cross-connected section, its output connected to an output terminal OUT, and receives the power supply voltage VDDQ.
Further, as a related technology, a level shifter capable of reducing the power consumption by eliminating pass-through current is described in Patent Document 2.
Further, as a related technology, a level shifter that operates at high speed without using a latch structure for level shifting and that consumes low power is described in Patent Document 3.
[Patent Document 1] U.S. Pat. No. 4,845,381
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2004-363740A
[Patent Document 3] Japanese Patent Kokai Publication No. JP-P2004-7821 A